An EEPROM is a semiconductor device that contains a group of memory cells for storing an electrically alterable pattern of binary information in a non-volatile manner. Each EEPROM cell typically centers around an MOS-type FET having a floating gate and one or more control gates. The floating gate is fully surrounded by electrically insulating material.
Using mechanisms such as hot carrier injection and electron energy-barrier tunneling, various levels of electronic charge can be placed on the floating gate. Due to the surrounding insulation, the charge stays on the floating gate for long periods of time. This enables the threshold voltage of the FET to be adjusted in a semi-permanent way.
Directly after fabrication, there is substantially no charge on the floating gate. Starting from this virgin state, the cell is "programmed" to one binary value by supplying the floating gate with a high level of charge of a given polarity. The cell is "erased" to the opposite binary value by removing a large amount, preferably all, of the charge from the floating gate. Charge of opposite polarity may even be placed on the floating gate to overerase the cell. In any case, the cell can now be alternately programmed and erased by adjusting the charge on the floating gate in the preceding way.
The charge states for programming and erasure establish two materially different levels for the threshold voltage. To read the stored information, a voltage that lies between the two threshold levels is suitably applied to the cell. The floating-gate FET is then either capable of conducting current or incapable of doing so depending respectively on whether the floating gate is at the erased or programmed condition. This indicates which binary value is stored in the cell.
Numerous types of structures have been developed for floating-gate EEPROM cells. The simplest structures use a single control gate to accomplish the read, program, and erase operations. In more advanced structures, programming and reading are performed with a main control gate commonly referred to simply as the control gate. Erasure is done with a separate control gate generally termed the erase gate. Both control gates lie at least partially over the floating gate. This "double-control-gate" arrangement helps to improve charge retention and EEPROM lifetime. The erase voltage may also be reduced.
In U.S. Pat. No. 4,119,995, Simko describes such a double-control-gate EEPROM cell. Simko's floating-gate FET is an n-channel device. During erasure, electrons tunnel from the floating gate to the erase gate. The tunneling is facilitated by providing the upper surface of the floating gate with sharp protuberances. These "asperities" enhance the electric field along the upper surface of the floating gate so as to reduce the necessary erase voltage. Simko discloses that (at least part of) the upper lateral edge of his floating gate is in the form of a cusp-shaped asperity.
Hazani, U.S. Pat. No. 4,763,229, describes another n-channel double-control-gate EEPROM cell in which asperities lie along the upper surface of the portion of the floating gate located below the erase gate but not along the upper surface of the remainder of the floating gate. Consequently, the upper surface of the portion of the floating gate separated from the control gate only by insulating material does not have any asperities. This floating-gate structure is advantageous because it improves tunneling during erasure while minimizing the possibility of undesired tunneling at other times.
In Hazani's fabrication process, recessed field-oxide regions are formed along part of the upper surface of a p-type monocrystalline silicon ("monosilicon") substrate. N-type source and drain zones for the FET are then created in the substrate along its upper surface. A thin gate dielectric layer which adjoins the field oxide is formed along the upper surface of the substrate. A patterned electrically conductive first polycrystalline silicon ("polysilicon") layer that eventually serves as the floating gate is provided over the gate dielectric and over an adjoining section of the field oxide.
Hazani subsequently performs a wet oxidation to grow a main silicon layer along the upper and lateral surfaces of the first polysilicon layer. The oxidation is done in such a way that asperities are produced along the upper surface of the remaining first polysilicon. A patterned electrically conductive second polysilicon layer, part of which later becomes the erase gate, is formed on a portion of the main oxide layer located above the field oxide.
The portion of the main oxide layer not covered by the second polysilicon layer is removed with an etchant that attacks silicon dioxide much more than polysilicon. In this way, the second polysilicon largely prevents asperities on the underlying portion of the first polysilicon from being etched. At this point, Hazani says that he ion implants phosphorus or arsenic to planarize the upper surface of the exposed portion of the first polysilicon and to remove the asperities located on that part of the first polysilicon.
Next, Hazani performs an oxidation to grow a further silicon dioxide layer along the upper surface of the structure. The remainder of the first polysilicon forms the floating gate. The portion of the remaining second polysilicon located above the floating gate is the erase gate.
A patterned third polysilicon layer is provided on the further oxide layer. The third polysilicon layer lies above the floating gate and extends laterally beyond at over a select portion of Hazani's FET. Part of the third polysilicon serves as the control gate. Conventional processing is then employed to complete cell fabrication.
Hazani's EEPROM cell structure offers excellent charge transfer and retention capabilities at relatively low erase voltage. However, it is not clear that the asperity-removal portion of his fabrication process will actually be successful in removing the indicated part of the asperities. Furthermore, the ion implant used in the asperity removal inevitably entails a critical lithographic masking step to avoid damaging the select portion of the FET. This is disadvantageous. Because the first polysilicon was made electrically conductive prior to the asperity-removal implant, there is a significantly increased risk that this implant will degrade the integrity of the gate dielectric. Consequently, it is highly desirable to have a better selective asperity-definition technique that can be used to fabricate an EEPROM having the general characteristics of Hazani's device.